Sutajio Kosagi Precursor
mobile/sutajiokosagi/precursor (platform)
| Property | Description |
|---|---|
| Manufacturer | Sutajio Kosagi |
| Model | Precursor |
| Year | 2021 |
| Max CPU | Integrated VexRiscV |
| Max RAM | 16 MB Onboard off-chip SRAM. Used in addition to 128 KB on-chip SRAM. |
| Image | Precursor, credit Sutajio Kosagi (https://media.telefonicatech.com/telefonicatech/uploads/2023/10/precursor-huang-bunnie-device.jpg) |
| Software: User-Facing Environment | Free |
| Software: Operating System | Free (Xous) |
| Software: Bootloader/Recovery | Free (loader) |
| Firmware: Trusted Execution Environment (e.g. x86 SMM) | Not Present |
| Firmware: Late Boot/Payload | No FW except bootloader/BROM |
| Firmware: Platform Initialization | Free |
| Firmware: Graphics Initialization | Free |
| Firmware: Memory Initialization | Free |
| Firmware: Early Boot (incl. RoT) | No FW except bootloader/BROM |
| Firmware: Boot ROM | Free |
| Firmware Signing | Available, user-controlled |
| CPU Microcode | Not Present The ed25519 engine is microcoded, but the CPUs are not. |
| Management Coprocessor: Firmware | Not Present |
| Network Interface: Internal Firmware | Proprietary (WF200 WLAN) |
| Network Interface: Host-Loaded Firmware | Proprietary, can disable WLAN |
| Security Coprocessor: Firmware | Free (FPGA crypto engine) |
| Embedded Controller: Firmware | Free (betrusted-ec) |
| Hardware: Board Electrical Schematic | Free |
| Hardware: Board PCB Design | Free |
| Hardware: CPU Instruction Set | Free (RISC-V) |
| Hardware: CPU/SoC Implementation | Free soft core, prop. FPGA (FPGA, VexRISC-V) |
| Hardware: CPU/SoC Synthesis Toolchain | Free for EC, prop. for main core |
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