AMD Coreboot on fam15h/fam10h
template/15hcoreboot (platform)
| Property | Description |
|---|---|
| Manufacturer | AMD |
| Model | Coreboot on fam15h/fam10h |
| Year | Undefined |
| Max CPU | Undefined |
| Max RAM | Undefined |
| Image | AMD logo, credit AMD (http://1.bp.blogspot.com/-T9mmhti40Wo/UAFdCQjPZqI/AAAAAAAAAL4/6fxKBk2BZ8E/s1600/Amd+2.png) |
| Software: User-Facing Environment | Free |
| Software: Operating System | Free |
| Software: Bootloader/Recovery | Free |
| Firmware: Persistent Privileged Code (e.g. x86 SMM) | Free (Coreboot) |
| Firmware: Late Boot/Payload | Free (Coreboot) |
| Firmware: Platform Initialization | Free (Coreboot) |
| Firmware: Memory Initialization | Free (Coreboot) |
| Firmware: Early Boot (incl. RoT) | Free (Coreboot) |
| Firmware: Boot ROM | None x86 CPUs don't have true "software" boot ROMs in mask ROM (such as those in many ARM SoCs).
Most x86 platforms map the firmware in SPI flash directly into address space at the reset vector, where it can be executed in-place. Prior to this, some early
initialization may be performed by the ROM microcode, or by coprocessors (such as the ME/PSP) if present. |
| Firmware Signing | None |
| CPU Microcode | Proprietary, RE possible on fam10h CPUs On K10-microarchitecture CPUs (e.g. fam10h Opterons of the 4100- and
6100-series, microcode updates are neither signed nor encrypted, and have been succesfully modified (modifying the behaviour of instructions to insert and trigger
proof-of-concept backdoors) as part of RUB-Sysstat's "Microcode" project (paper,
GitHub). On later CPUs (e.g. 6200/6300-series Opterons), microcode is encrypted. |
| Management Coprocessor: Firmware | None |
| Communications Coprocessor: Internal Firmware | Undefined |
| Communications Coprocessor: Host-Loaded Firmware | Undefined |
| Security Coprocessor: Firmware | Undefined |
| Embedded Controller: Firmware | Undefined |
| Hardware: Board Electrical Schematic | Proprietary |
| Hardware: Board PCB Design | Proprietary |
| Hardware: CPU Instruction Set | Proprietary (x86_64) |
| Hardware: CPU/SoC Implementation | Proprietary (AMD K10/Bulldozer/Piledriver) |
| Hardware: CPU/SoC Synthesis Toolchain | Proprietary |
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