AMD Socket AM3+
template/am3plus (platform)
| Property | Description |
|---|---|
| Manufacturer | AMD |
| Model | Socket AM3+ |
| Year | Undefined |
| Max CPU | AMD FX-9590 |
| Max RAM | 64GB |
| Image | AMD logo, credit AMD (http://1.bp.blogspot.com/-T9mmhti40Wo/UAFdCQjPZqI/AAAAAAAAAL4/6fxKBk2BZ8E/s1600/Amd+2.png) |
| Software: User-Facing Environment | Free |
| Software: Operating System | Free |
| Software: Bootloader/Recovery | Free |
| Firmware: Trusted Execution Environment (e.g. x86 SMM) | Undefined |
| Firmware: Late Boot/Payload | Undefined |
| Firmware: Platform Initialization | Undefined |
| Firmware: Graphics Initialization | Undefined |
| Firmware: Memory Initialization | Undefined |
| Firmware: Early Boot (incl. RoT) | Undefined |
| Firmware: Boot ROM | None x86 CPUs don't have true "software" boot ROMs in mask ROM (such as those in many ARM SoCs).
Most x86 platforms map the firmware in SPI flash directly into address space at the reset vector, where it can be executed in-place. Prior to this, some early
initialization may be performed by the ROM microcode, or by coprocessors (such as the ME/PSP) if present. |
| Firmware Signing | None |
| CPU Microcode | Proprietary |
| Management Coprocessor: Firmware | None |
| Network Interface: Internal Firmware | Undefined |
| Network Interface: Host-Loaded Firmware | Undefined |
| Security Coprocessor: Firmware | Undefined |
| Embedded Controller: Firmware | Undefined |
| Hardware: Board Electrical Schematic | Proprietary |
| Hardware: Board PCB Design | Proprietary |
| Hardware: CPU Instruction Set | Proprietary (x86_64) |
| Hardware: CPU/SoC Implementation | Proprietary (AMD K10/Bulldozer/Piledriver) |
| Hardware: CPU/SoC Synthesis Toolchain | Proprietary |
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