Intel FSP Platform
template/fsp (platform)
| Property | Description |
|---|---|
| Manufacturer | Intel |
| Model | FSP Platform |
| Image | Intel Logo, credit Intel (https://logodownload.org/wp-content/uploads/2014/04/intel-logo-1-1.png) |
| Software: User-Facing Environment | Free |
| Software: Operating System | Free |
| Software: Bootloader/Recovery | Free |
| Firmware: Persistent Privileged Code (e.g. x86 SMM) | Proprietary, incl. FSP code |
| Firmware: Late Boot/Payload | Proprietary (Vendor UEFI) |
| Firmware: Memory Initialization | Proprietary (Intel FSP) |
| Firmware: Early Boot | Proprietary (Vendor UEFI) |
| Firmware: Boot ROM | None x86 CPUs don't have true "software" boot ROMs in mask ROM (such as those in many ARM SoCs).
Most x86 platforms map the firmware in SPI flash directly into address space at the reset vector, where it can be executed in-place. Prior to this, some early
initialization may be performed by the ROM microcode, or by coprocessors (such as the ME/PSP) if present. |
| Firmware Signing | Undefined |
| CPU Microcode | Proprietary All current x86 CPUs use proprietary microcode, stored in mask ROM in the CPU itself.
Additional updates to this microcode can be temporarily loaded by firmware and/or the OS. |
| Management Coprocessor: Firmware | Proprietary, partially disabled (ME Gen3) On ME versions 11 and above (Skylake and newer), sometimes called "ME Generation 3", less of the ME firmware can be removed or disabled while still leaving the
system operational. Approximately 300 kB of the original 2 - 7 MB binary, consisting of four regions (rbe, kernel, syslib, and bup) are required. However, normal
ME operation can still be disabled. The AltMeDisable ("HAP bit") can be used on these MEs. |
| Communications Coprocessor: Internal Firmware | Undefined |
| Communications Coprocessor: Host-Loaded Firmware | Undefined |
| Security Coprocessor: Firmware | Undefined |
| Embedded Controller: Firmware | Undefined |
| Hardware: Board Electrical Schematic | Proprietary |
| Hardware: Board PCB Design | Proprietary |
| Hardware: CPU Instruction Set | Proprietary (x86_64) |
| Hardware: CPU/SoC Implementation | Proprietary (Intel Skylake or newer) |
| Hardware: CPU/SoC Synthesis Toolchain | Proprietary |
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