Intel GM45-Chipset System
template/gm45 (platform)
| Property | Description |
|---|---|
| Manufacturer | Intel |
| Model | GM45-Chipset System |
| Year | Undefined |
| Max CPU | Undefined |
| Max RAM | Undefined |
| Image | Intel Logo, credit Intel (https://logodownload.org/wp-content/uploads/2014/04/intel-logo-1-1.png) |
| Software: User-Facing Environment | Free |
| Software: Operating System | Free |
| Software: Bootloader/Recovery | Free |
| Firmware: Persistent Privileged Code (e.g. x86 SMM) | Undefined |
| Firmware: Late Boot/Payload | Undefined |
| Firmware: Platform Initialization | Undefined |
| Firmware: Memory Initialization | Undefined |
| Firmware: Early Boot (incl. RoT) | Undefined |
| Firmware: Boot ROM | None x86 CPUs don't have true "software" boot ROMs in mask ROM (such as those in many ARM SoCs).
Most x86 platforms map the firmware in SPI flash directly into address space at the reset vector, where it can be executed in-place. Prior to this, some early
initialization may be performed by the ROM microcode, or by coprocessors (such as the ME/PSP) if present. |
| Firmware Signing | None |
| CPU Microcode | Proprietary All current x86 CPUs use proprietary microcode, stored in mask ROM in the CPU itself.
Additional updates to this microcode can be temporarily loaded by firmware and/or the OS. |
| Management Coprocessor: Firmware | Proprietary, fully removable (ME Gen1) On ME versions 5 and below (prior to Nehalem), the ME can be entirely disabled with flash descriptor configuration, and its firmware
can safely be entirely removed from the flash image. |
| Communications Coprocessor: Internal Firmware | Undefined |
| Communications Coprocessor: Host-Loaded Firmware | Undefined |
| Security Coprocessor: Firmware | Undefined |
| Embedded Controller: Firmware | Undefined |
| Hardware: Board Electrical Schematic | Proprietary |
| Hardware: Board PCB Design | Proprietary |
| Hardware: CPU Instruction Set | Proprietary (x86_64) |
| Hardware: CPU/SoC Implementation | Proprietary (Intel Merom/Penryn/Core 2 Quad) |
| Hardware: CPU/SoC Synthesis Toolchain | Proprietary |
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