| Legend: | |||||||
|---|---|---|---|---|---|---|---|
| Free | Proprietary | Mixed Free and Proprietary | Proprietary, but fully disableable | Proprietary, but partial info/RE work available | Unknown | Undefined | None or N/A - feature/system not present |
| Property | Description |
|---|---|
| Manufacturer | Undefined |
| Model | Optional TPM |
| Year | Undefined |
| Max CPU | Undefined |
| Max RAM | Undefined |
| Image | Undefined |
| Software: User-Facing Environment | Undefined |
| Software: Operating System | Undefined |
| Software: Bootloader/Recovery | Undefined |
| Firmware: Persistent Privileged Code (e.g. x86 SMM) | Undefined |
| Firmware: Late Boot/Payload | Undefined |
| Firmware: Platform Initialization | Undefined |
| Firmware: Memory Initialization | Undefined |
| Firmware: Early Boot (incl. RoT) | Undefined |
| Firmware: Boot ROM | Undefined |
| Firmware Signing | Undefined |
| CPU Microcode | Undefined |
| Management Coprocessor: Firmware | Undefined |
| Communications Coprocessor: Internal Firmware | Undefined |
| Communications Coprocessor: Host-Loaded Firmware | Undefined |
| Security Coprocessor: Firmware | No TPM included, likely proprietary if added |
| Embedded Controller: Firmware | Undefined |
| Hardware: Board Electrical Schematic | Undefined |
| Hardware: Board PCB Design | Undefined |
| Hardware: CPU Instruction Set | Undefined |
| Hardware: CPU/SoC Implementation | Undefined |
| Hardware: CPU/SoC Synthesis Toolchain | Undefined |