| Legend: | |||||||
|---|---|---|---|---|---|---|---|
| Free | Proprietary | Mixed Free and Proprietary | Proprietary, but fully disableable | Proprietary, but partial info/RE work available | Unknown | Undefined | Not Present |
| Property | Description |
|---|---|
| Manufacturer | Rockchip |
| Model | SoC Device |
| Year | Undefined |
| Max CPU | Undefined |
| Max RAM | Undefined |
| Image | Undefined |
| Software: User-Facing Environment | Free |
| Software: Operating System | Free |
| Software: Bootloader/Recovery | Free (uboot) |
| Firmware: Trusted Execution Environment (e.g. x86 SMM) | Undefined |
| Firmware: Late Boot/Payload | Free (uboot) |
| Firmware: Platform Initialization | Free (uboot) |
| Firmware: Graphics Initialization | Free (uboot) |
| Firmware: Memory Initialization | Proprietary (DDR init blob) |
| Firmware: Early Boot (incl. RoT) | Free (uboot SPL) |
| Firmware: Boot ROM | Proprietary |
| Firmware Signing | Not Present |
| CPU Microcode | Not microcoded |
| Management Coprocessor: Firmware | Not Present |
| Network Interface: Internal Firmware | Undefined |
| Network Interface: Host-Loaded Firmware | Undefined |
| Security Coprocessor: Firmware | Undefined |
| Embedded Controller: Firmware | Undefined |
| Hardware: Board Electrical Schematic | Undefined |
| Hardware: Board PCB Design | Undefined |
| Hardware: CPU Instruction Set | Proprietary (Arm) |
| Hardware: CPU/SoC Implementation | Proprietary |
| Hardware: CPU/SoC Synthesis Toolchain | Proprietary |