| Legend: | |||||||
|---|---|---|---|---|---|---|---|
| Free | Proprietary | Mixed Free and Proprietary | Proprietary, but fully disableable | Proprietary, but partial info/RE work available | Unknown | Undefined | None or N/A - feature/system not present |
| Property | Description |
|---|---|
| Manufacturer | MSI |
| Model | PRO Z690-A DDR4 |
| Year | 2021 |
| Max CPU | Intel Core i9-14900KF |
| Max RAM | 128GB 4x32GB DDR4-3200 DIMM |
| Image | Intel Logo, credit Intel (https://logodownload.org/wp-content/uploads/2014/04/intel-logo-1-1.png) |
| Software: User-Facing Environment | Free |
| Software: Operating System | Free |
| Software: Bootloader/Recovery | Free |
| Firmware: Persistent Privileged Code (e.g. x86 SMM) | Free (Coreboot) This is an FSP platform. However, with the exception of the (optional) FSP-I on certain very
recent Xeon platforms, no FSP components run in SMM. |
| Firmware: Late Boot/Payload | Free (EDK2, etc.) |
| Firmware: Platform Initialization | Mixed, Coreboot w/ prop. FSP-S |
| Firmware: Memory Initialization | Proprietary (FSP-M) |
| Firmware: Early Boot (incl. RoT) | Free (Coreboot) |
| Firmware: Boot ROM | None x86 CPUs don't have true "software" boot ROMs in mask ROM (such as those in many ARM SoCs).
Most x86 platforms map the firmware in SPI flash directly into address space at the reset vector, where it can be executed in-place. Prior to this, some early
initialization may be performed by the ROM microcode, or by coprocessors (such as the ME/PSP) if present. |
| Firmware Signing | For ME only ME Gen4 and newer are not vulnerable to
CVE-2017-5705 |
| CPU Microcode | Proprietary All current x86 CPUs use proprietary microcode, stored in mask ROM in the CPU itself.
Additional updates to this microcode can be temporarily loaded by firmware and/or the OS. |
| Management Coprocessor: Firmware | Proprietary, partially disabled (ME Gen4+) On ME version 12 and above (some Coffee Lake, all post-Coffee-Lake), sometimes called "IFWI ME" or "ME Generation 4" or later, module removal (as was done
with earlier MEs) is not currently known to be possible. However, the AltMeDisable ("HAP bit") can still be used on these MEs. |
| Communications Coprocessor: Internal Firmware | No WLAN card included, likely proprietary if added |
| Communications Coprocessor: Host-Loaded Firmware | Dependent on WLAN card installed |
| Security Coprocessor: Firmware | No TPM included, likely proprietary if added |
| Embedded Controller: Firmware | Proprietary (NCT6687 EC) Unusually for use in a desktop, the Nuvoton NCT6687 used on these boards is a sort of hybrid of a
conventional, host-configured Super I/O and a programmable EC. Though it provides SIO-like features, it also loads its own EC firmware from a separate,
dedicated flash chip. |
| Hardware: Board Electrical Schematic | Proprietary |
| Hardware: Board PCB Design | Proprietary, but boardview often available |
| Hardware: CPU Instruction Set | Proprietary (x86_64) |
| Hardware: CPU/SoC Implementation | Proprietary (Intel Alder Lake/Raptor Lake) |
| Hardware: CPU/SoC Synthesis Toolchain | Proprietary |