Lenovo IdeaPad G505s
laptop/lenovo/g505s (platform)
| Property | Description |
|---|---|
| Manufacturer | Lenovo |
| Model | IdeaPad G505s |
| Year | 2013 |
| Max CPU | AMD A10-6800K |
| Max RAM | 32GB 2x16GB DDR3-1600 SODIMM |
| Image | AMD logo, credit AMD (http://1.bp.blogspot.com/-T9mmhti40Wo/UAFdCQjPZqI/AAAAAAAAAL4/6fxKBk2BZ8E/s1600/Amd+2.png) |
| Software: User-Facing Environment | Free |
| Software: Operating System | Free |
| Software: Bootloader/Recovery | Free |
| Firmware: Persistent Privileged Code (e.g. x86 SMM) | Free (Coreboot) |
| Firmware: Late Boot/Payload | Free (Coreboot) |
| Firmware: Platform Initialization | Free (Coreboot) |
| Firmware: Memory Initialization | Free (Coreboot) |
| Firmware: Early Boot (incl. RoT) | Free (Coreboot) |
| Firmware: Boot ROM | None x86 CPUs don't have true "software" boot ROMs in mask ROM (such as those in many ARM SoCs).
Most x86 platforms map the firmware in SPI flash directly into address space at the reset vector, where it can be executed in-place. Prior to this, some early
initialization may be performed by the ROM microcode, or by coprocessors (such as the ME/PSP) if present. |
| Firmware Signing | None |
| CPU Microcode | Proprietary |
| Management Coprocessor: Firmware | None |
| Communications Coprocessor: Internal Firmware | WLAN proprietary, but card is removable |
| Communications Coprocessor: Host-Loaded Firmware | Unnecessary with some cards (e.g. ath9k) |
| Security Coprocessor: Firmware | None or N/A - feature/system not present |
| Embedded Controller: Firmware | Proprietary |
| Hardware: Board Electrical Schematic | Proprietary, but often available online |
| Hardware: Board PCB Design | Proprietary, but boardview often available |
| Hardware: CPU Instruction Set | Proprietary (x86_64) |
| Hardware: CPU/SoC Implementation | Proprietary (AMD Piledriver) |
| Hardware: CPU/SoC Synthesis Toolchain | Proprietary |
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