| Legend: | |||||||
|---|---|---|---|---|---|---|---|
| Free | Proprietary | Mixed Free and Proprietary | Proprietary, but fully disableable | Proprietary, but partial info/RE work available | Unknown | Undefined | Not Present |
| Property | Description |
|---|---|
| Manufacturer | ASUS |
| Model | KCMA-D8 |
| Year | 2010 |
| Max CPU | 2x AMD Opteron 4386 |
| Max RAM | 512GB 8x64GB DDR3-1600 ECC RDIMM |
| Image | AMD logo, credit AMD (http://1.bp.blogspot.com/-T9mmhti40Wo/UAFdCQjPZqI/AAAAAAAAAL4/6fxKBk2BZ8E/s1600/Amd+2.png) |
| Software: User-Facing Environment | Free |
| Software: Operating System | Free |
| Software: Bootloader/Recovery | Free |
| Firmware: Trusted Execution Environment (e.g. x86 SMM) | Free (coreboot) |
| Firmware: Late Boot/Payload | Free (coreboot) |
| Firmware: Platform Initialization | Free (coreboot) |
| Firmware: Graphics Initialization | Free text-only (AST2050 native) Free native text-mode-only initialization (without an
Option ROM) is available for the ASpeed AST2050 BMC used for the onboard VGA on this board. Linux can then initialize the BMC's graphics (framebuffer) modes
for non-text output. If graphics are required earlier (e.g. for a bootsplash or GRUB framebuffer), the proprietary AST2050 Option ROM can be used instead. |
| Firmware: Memory Initialization | Free (coreboot) |
| Firmware: Early Boot (incl. RoT) | Free (coreboot) |
| Firmware: Boot ROM | None x86 CPUs don't have true "software" boot ROMs in mask ROM (such as those in many ARM SoCs).
Most x86 platforms map the firmware in SPI flash directly into address space at the reset vector, where it can be executed in-place. Prior to this, some early
initialization may be performed by the ROM microcode, or by coprocessors (such as the ME/PSP) if present. |
| Firmware Signing | None |
| CPU Microcode | Proprietary, RE possible on fam10h CPUs On K10-microarchitecture CPUs (e.g. fam10h Opterons of the 4100- and
6100-series, microcode updates are neither signed nor encrypted, and have been succesfully modified (modifying the behaviour of instructions to insert and trigger
proof-of-concept backdoors) as part of RUB-Sysstat's "Microcode" project (paper,
GitHub). On later CPUs (e.g. 6200/6300-series Opterons), microcode is encrypted. |
| Management Coprocessor: Firmware | None |
| Board Management Controller: Firmware | No OpenBMC port, proprietary ASMB4 flash removable |
| Network Interface: Internal Firmware | None, unless you install one |
| Network Interface: Host-Loaded Firmware | None, unless you install one |
| Security Coprocessor: Firmware | None, but has TPM header (TPM can be added) |
| Embedded Controller: Firmware | None, EC-like functions on BMC |
| Hardware: Board Electrical Schematic | Proprietary |
| Hardware: Board PCB Design | Proprietary, but boardview often available |
| Hardware: CPU Instruction Set | Proprietary (x86_64) |
| Hardware: CPU/SoC Implementation | Proprietary (AMD K10/Bulldozer/Piledriver) |
| Hardware: CPU/SoC Synthesis Toolchain | Proprietary |