Supermicro H8DGI
server/supermicro/h8dgi (platform-server)
| Property | Description |
|---|---|
| Manufacturer | Supermicro |
| Model | H8DGI |
| Year | 2010 |
| Max CPU | 2x AMD Opteron 6386 SE |
| Max RAM | 512GB, possibly 1TB 16x32GB DDR3-1600 ECC RDIMM. 16x64GB (for 1TB) may also be possible but is untested. |
| Image | AMD logo, credit AMD (http://1.bp.blogspot.com/-T9mmhti40Wo/UAFdCQjPZqI/AAAAAAAAAL4/6fxKBk2BZ8E/s1600/Amd+2.png) |
| Software: User-Facing Environment | Free |
| Software: Operating System | Free |
| Software: Bootloader/Recovery | Free |
| Firmware: Trusted Execution Environment (e.g. x86 SMM) | Free (coreboot) |
| Firmware: Late Boot/Payload | Free (coreboot) |
| Firmware: Platform Initialization | Free (coreboot) |
| Firmware: Graphics Initialization | Proprietary if VGA used (WPCM450 Option ROM) The Nuvoton WPCM450 BMC used by the
Supermicro H8* boards provides the onboard VGA output with its integrated Matrox G200eW display adapter. Video output from these BMCs requires a
proprietary Option ROM. If the onboard VGA is not required, this Option ROM can be excluded. |
| Firmware: Memory Initialization | Free (coreboot) |
| Firmware: Early Boot (incl. RoT) | Free (coreboot) |
| Firmware: Boot ROM | None x86 CPUs don't have true "software" boot ROMs in mask ROM (such as those in many ARM SoCs).
Most x86 platforms map the firmware in SPI flash directly into address space at the reset vector, where it can be executed in-place. Prior to this, some early
initialization may be performed by the ROM microcode, or by coprocessors (such as the ME/PSP) if present. |
| Firmware Signing | None |
| CPU Microcode | Proprietary, RE possible on fam10h CPUs On K10-microarchitecture CPUs (e.g. fam10h Opterons of the 4100- and
6100-series, microcode updates are neither signed nor encrypted, and have been succesfully modified (modifying the behaviour of instructions to insert and trigger
proof-of-concept backdoors) as part of RUB-Sysstat's "Microcode" project (paper,
GitHub). On later CPUs (e.g. 6200/6300-series Opterons), microcode is encrypted. |
| Management Coprocessor: Firmware | None |
| Board Management Controller: Firmware | Proprietary BMC, disableable by jumper |
| Network Interface: Internal Firmware | None, unless you install one |
| Network Interface: Host-Loaded Firmware | None, unless you install one |
| Security Coprocessor: Firmware | None, but has TPM header (TPM can be added) |
| Embedded Controller: Firmware | None, EC-like functions on BMC |
| Hardware: Board Electrical Schematic | Proprietary |
| Hardware: Board PCB Design | Proprietary |
| Hardware: CPU Instruction Set | Proprietary (x86_64) |
| Hardware: CPU/SoC Implementation | Proprietary (AMD K10/Bulldozer/Piledriver) |
| Hardware: CPU/SoC Synthesis Toolchain | Proprietary |
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