Intel coreboot on Kaby Lake System
template/kabylakecoreboot (platform)
| Property | Description |
|---|---|
| Manufacturer | Intel |
| Model | coreboot on Kaby Lake System |
| Year | Undefined |
| Max CPU | Undefined |
| Max RAM | Undefined |
| Image | Intel Logo, credit Intel (https://logodownload.org/wp-content/uploads/2014/04/intel-logo-1-1.png) |
| Software: User-Facing Environment | Free |
| Software: Operating System | Free |
| Software: Bootloader/Recovery | Free |
| Firmware: Trusted Execution Environment (e.g. x86 SMM) | Free (coreboot) This is an FSP platform. However, with the exception of the (optional) FSP-I on certain very
recent Xeon platforms, no FSP components run in SMM. |
| Firmware: Late Boot/Payload | Free (EDK2, etc.) |
| Firmware: Platform Initialization | Mixed, coreboot w/ prop. FSP-S |
| Firmware: Graphics Initialization | Free (libgfxinit) |
| Firmware: Memory Initialization | Proprietary (FSP-M) |
| Firmware: Early Boot (incl. RoT) | Free (coreboot) |
| Firmware: Boot ROM | None x86 CPUs don't have true "software" boot ROMs in mask ROM (such as those in many ARM SoCs).
Most x86 platforms map the firmware in SPI flash directly into address space at the reset vector, where it can be executed in-place. Prior to this, some early
initialization may be performed by the ROM microcode, or by coprocessors (such as the ME/PSP) if present. |
| Firmware Signing | For ME Only, Boot Guard disabled |
| CPU Microcode | Proprietary All current x86 CPUs use proprietary microcode, stored in mask ROM in the CPU itself.
Additional updates to this microcode can be temporarily loaded by firmware and/or the OS. |
| Management Coprocessor: Firmware | Proprietary, partially disabled (ME Gen3) On ME version 11 specifically (Skylake, Kaby Lake, and some Coffee Lake), sometimes called "ME Generation 3", less of the ME firmware can be removed or
disabled while still leaving the system operational than on earlier versions. Approximately 300 kB of the original 2 - 7 MB binary, consisting of four regions
(rbe, kernel, syslib, and bup) are required. The AltMeDisable ("HAP") bit can also be used on these MEs. |
| Network Interface: Internal Firmware | Undefined |
| Network Interface: Host-Loaded Firmware | Undefined |
| Security Coprocessor: Firmware | Undefined |
| Embedded Controller: Firmware | Undefined |
| Hardware: Board Electrical Schematic | Proprietary |
| Hardware: Board PCB Design | Proprietary |
| Hardware: CPU Instruction Set | Proprietary (x86_64) |
| Hardware: CPU/SoC Implementation | Proprietary (Intel) |
| Hardware: CPU/SoC Synthesis Toolchain | Proprietary |
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