| Legend: | |||||||
|---|---|---|---|---|---|---|---|
| Free | Proprietary | Mixed Free and Proprietary | Proprietary, but fully disableable | Proprietary, but partial info/RE work available | Unknown | Undefined | Not Present |
| Property | Description |
|---|---|
| Manufacturer | Lenovo |
| Model | ThinkPad X140e |
| Year | 2013 |
| Max CPU | AMD A4-5000 |
| Max RAM | 16GB 2x8GB DDR3-1600 SODIMM |
| Image | AMD logo, credit AMD (http://1.bp.blogspot.com/-T9mmhti40Wo/UAFdCQjPZqI/AAAAAAAAAL4/6fxKBk2BZ8E/s1600/Amd+2.png) |
| Software: User-Facing Environment | Free |
| Software: Operating System | Free |
| Software: Bootloader/Recovery | Free |
| Firmware: Trusted Execution Environment (e.g. x86 SMM) | Free (coreboot) |
| Firmware: Late Boot/Payload | Free (coreboot) |
| Firmware: Platform Initialization | Free (coreboot) |
| Firmware: Graphics Initialization | Proprietary, some RE work (AtomBIOS) The AtomBIOS VBIOS used for Trinity and Richland's
integrated graphics is a proprietary Option ROM. However, some reverse-engineering is available from the
openatom project, and in AtomBiosRunner. |
| Firmware: Memory Initialization | Free (coreboot) |
| Firmware: Early Boot (incl. RoT) | Free (coreboot) |
| Firmware: Boot ROM | None x86 CPUs don't have true "software" boot ROMs in mask ROM (such as those in many ARM SoCs).
Most x86 platforms map the firmware in SPI flash directly into address space at the reset vector, where it can be executed in-place. Prior to this, some early
initialization may be performed by the ROM microcode, or by coprocessors (such as the ME/PSP) if present. |
| Firmware Signing | None |
| CPU Microcode | Proprietary All current x86 CPUs use proprietary microcode, stored in mask ROM in the CPU itself.
Additional updates to this microcode can be temporarily loaded by firmware and/or the OS. |
| Management Coprocessor: Firmware | Proprietary (SMU Firmware) The SMU (System Management Unit) is a microcontroller inside AMD SoCs/APUs that handles
low-level platform management: power, clocks, voltage, thermal control, power-gating, and related sensors and interrupts. The firmware for this
microcontroller is a blob,
included as a large array in the Family 15h AGESA source. Orochi platforms do not require this blob. |
| Network Interface: Internal Firmware | WLAN proprietary, but card is removable |
| Network Interface: Host-Loaded Firmware | Unnecessary with some cards (e.g. ath9k) |
| Security Coprocessor: Firmware | Not Present |
| Embedded Controller: Firmware | Proprietary |
| Hardware: Board Electrical Schematic | Proprietary, but often available online |
| Hardware: Board PCB Design | Proprietary, but boardview often available |
| Hardware: CPU Instruction Set | Proprietary (x86_64) |
| Hardware: CPU/SoC Implementation | Proprietary (AMD Jaguar) |
| Hardware: CPU/SoC Synthesis Toolchain | Proprietary |