| Legend: | |||||||
|---|---|---|---|---|---|---|---|
| Free | Proprietary | Mixed Free and Proprietary | Proprietary, but fully disableable | Proprietary, but partial info/RE work available | Unknown | Undefined | Not Present |
| Property | Description |
|---|---|
| Manufacturer | Supermicro |
| Model | X10SLM+-F |
| Year | 2013 |
| Max CPU | 1x Intel Core i7-4790k |
| Max RAM | 32GB 4x8GB DDR3-1600 ECC RDIMM |
| Image | Intel Logo, credit Intel (https://logodownload.org/wp-content/uploads/2014/04/intel-logo-1-1.png) |
| Software: User-Facing Environment | Free |
| Software: Operating System | Free |
| Software: Bootloader/Recovery | Free |
| Firmware: Trusted Execution Environment (e.g. x86 SMM) | Free (coreboot) |
| Firmware: Late Boot/Payload | Free (SeaBIOS, etc.) |
| Firmware: Platform Initialization | Free (coreboot) |
| Firmware: Graphics Initialization | Free (libgfxinit) |
| Firmware: Memory Initialization | Free (coreboot Haswell NRI) ECC memory is not currently supported by Haswell NRI. ECC memory users currently
need to use the proprietary Intel MRC instead. |
| Firmware: Early Boot (incl. RoT) | Free (coreboot) |
| Firmware: Boot ROM | None x86 CPUs don't have true "software" boot ROMs in mask ROM (such as those in many ARM SoCs).
Most x86 platforms map the firmware in SPI flash directly into address space at the reset vector, where it can be executed in-place. Prior to this, some early
initialization may be performed by the ROM microcode, or by coprocessors (such as the ME/PSP) if present. |
| Firmware Signing | ME only, theoretically defeatable ME Gen2 is reportedly also vulnerable to
CVE-2017-5705, which has been used on ME Gen3 to
defeat Boot Guard. However, Deguard does not currently support ME Gen2, and no other
practical application for CVE-2017-5705 is currently known. |
| CPU Microcode | Proprietary All current x86 CPUs use proprietary microcode, stored in mask ROM in the CPU itself.
Additional updates to this microcode can be temporarily loaded by firmware and/or the OS. |
| Management Coprocessor: Firmware | Proprietary, mostly disabled (ME Gen2) On ME versions between 6 through 10 (Nehalem to Broadwell), sometimes called "ME Generation 2", nearly the entire ME image can be removed, leaving only two modules - ROMP and BUP - totaling 90 kB out of a normal 1.5 - 5 MB.
With these modules removed, the ME remains in its BUP state and does not execute its kernel or normal ME functions, leaving it effectively disabled.
The AltMeDisable ("HAP") bit can also be used on these MEs. |
| Board Management Controller: Firmware | Unclear if BMC can be disabled |
| Network Interface: Internal Firmware | None, unless you install one |
| Network Interface: Host-Loaded Firmware | None, unless you install one |
| Security Coprocessor: Firmware | None, but has TPM header (TPM can be added) |
| Embedded Controller: Firmware | Not Present |
| Hardware: Board Electrical Schematic | Proprietary |
| Hardware: Board PCB Design | Proprietary |
| Hardware: CPU Instruction Set | Proprietary (x86_64) |
| Hardware: CPU/SoC Implementation | Proprietary (Intel Haswell) |
| Hardware: CPU/SoC Synthesis Toolchain | Proprietary |