Supermicro X10SLM+-F
server/supermicro/x10 (platform)
| Property | Description |
|---|---|
| Manufacturer | Supermicro |
| Model | X10SLM+-F |
| Year | 2013 |
| Max CPU | 1x Intel Core i7-4790k |
| Max RAM | 32GB 4x8GB DDR3-1600 ECC RDIMM |
| Image | Intel Logo, credit Intel (https://logodownload.org/wp-content/uploads/2014/04/intel-logo-1-1.png) |
| Software: User-Facing Environment | Free |
| Software: Operating System | Free |
| Software: Bootloader/Recovery | Free |
| Firmware: Persistent Privileged Code (e.g. x86 SMM) | Free (Coreboot) |
| Firmware: Late Boot/Payload | Free (SeaBIOS, etc.) |
| Firmware: Platform Initialization | Free (Coreboot) |
| Firmware: Memory Initialization | Free (Coreboot Haswell NRI) ECC memory is not currently supported by Haswell NRI. ECC memory users currently
need to use the proprietary Intel MRC instead. |
| Firmware: Early Boot (incl. RoT) | Free (Coreboot) |
| Firmware: Boot ROM | None x86 CPUs don't have true "software" boot ROMs in mask ROM (such as those in many ARM SoCs).
Most x86 platforms map the firmware in SPI flash directly into address space at the reset vector, where it can be executed in-place. Prior to this, some early
initialization may be performed by the ROM microcode, or by coprocessors (such as the ME/PSP) if present. |
| Firmware Signing | For ME Only |
| CPU Microcode | Proprietary All current x86 CPUs use proprietary microcode, stored in mask ROM in the CPU itself.
Additional updates to this microcode can be temporarily loaded by firmware and/or the OS. |
| Management Coprocessor: Firmware | ME mostly disabled, unclear if BMC can be disabled |
| Communications Coprocessor: Internal Firmware | None, unless you install one |
| Communications Coprocessor: Host-Loaded Firmware | None, unless you install one |
| Security Coprocessor: Firmware | None, but has TPM header (TPM can be added) |
| Embedded Controller: Firmware | None or N/A - feature/system not present |
| Hardware: Board Electrical Schematic | Proprietary |
| Hardware: Board PCB Design | Proprietary |
| Hardware: CPU Instruction Set | Proprietary (x86_64) |
| Hardware: CPU/SoC Implementation | Proprietary (Intel Haswell) |
| Hardware: CPU/SoC Synthesis Toolchain | Proprietary |
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